1. Field of the Invention
The present invention relates to a two-point frequency modulation apparatus, wireless transmitting apparatus, and wireless communication apparatus for use with communication equipments, such as mobile communication terminals including mobile telephones and base stations that communicate with the mobile communication terminals.
2. Description of the Related Art
Generally speaking, the PLL (Phase Locked Loop) modulation scheme for use with communication equipments is expected to realize low costs, low power consumption, excellent noise characteristics, and high modulation accuracy. To improve the modulation accuracy of this PLL modulation scheme, preferably, the PLL bandwidth (i.e. PLL bandwidth) is wider than the bandwidth of the modulation signal (i.e. modulation bandwidth).
However, widening the PLL bandwidth has the risk of deteriorating noise characteristics. So, the kind of two-point frequency modulation scheme is presently proposed whereby the PLL bandwidth is set narrower than the modulation bandwidth and the modulation in the PLL bandwidth and the modulation outside the PLL bandwidth are performed at two different points (see U.S. Pat. No. 6,211,747).
As shown in FIG. 1, a wideband modulation PLL system employing the above-noted two-point modulation scheme has: a PLL arrangement including voltage controlled oscillator (VCO) 1A, frequency divider 1B, phase comparator 1C, loop filter 1D, and adder 1E; modulation sensitivity table 4; delta-sigma modulator 5; D/A convertor 6; A/D convertor 7; adder 2; and controller 3.
VCO 1A in the PLL arrangement outputs an RF modulation signal. The oscillation frequency of the RF modulation signal changes in accordance with the voltage inputted in control voltage terminal Vt. Frequency divider 1B divides the frequency of the RF modulation signal outputted from VCO 1A. Phase comparator 1C compares the phase of the signal outputted from frequency divider 1B and the phase of the reference signal, and outputs a signal in accordance with the phase difference. Loop filter 1D equalizes the output signal of phase comparator 1C.
Modulation sensitivity table 4 outputs a modulation signal based on the modulation data. D/A convertor 6 adjusts the gain in accordance with a gain control signal outputted from controller 3 and converts the modulation signal outputted from modulation sensitivity table 4 into analogue voltage. The modulation signal outputted from modulation sensitivity table 4 and a channel selection signal outputted from controller 3 are added in adder 2, and delta-sigma modulator 5 applies delta-sigma modulation to the composite signal and generates the frequency division ratio in frequency divider 1B. A/D convertor 7 converts the voltage value inputted in control voltage terminal Vt into a digital value and outputs the data thus converted into a digital value, to controller 3.
However, in the wideband modulation PLL arrangement that employs the two-point modulation scheme, the signal input timings in two-point modulation need to be synchronized, and, when a difference between the input timings in two-point modulation develops, this may result in deterioration in modulation accuracy (e.g. EVM: Error Vector Magnitude).
For example, if a mobile telephone is made incorporating a wideband modulation PLL arrangement that employs the two-point modulation scheme in the communicating section, an input timing difference such as mentioned above occurs due to variations in the characteristics of individual electronic components.
In addition, when the mobile telephone is in use, the above input timing difference occurs when the battery is activated, when the power supply fluctuates, when the temperature changes, and in equivalent circumstances. In addition, if the mobile telephone employs the TDMA (Time Division Multiple Access) scheme, the above input timing difference occurs at the beginning of the time slot, when the power supply fluctuates, when the temperature changes, and in equivalent circumstances. Such input timing difference need to be corrected for improved modulation accuracy. However, there is not yet a particular method that enables input timing difference adjustment.